The present invention relates to arrangement verification apparatus and in particular to an arrangement verification apparatus for verifying the arrangement of control circuits that control block circuits comprising a semiconductor device.
When designing is carried out to arrange block circuits to be controlled comprising a semiconductor device and control circuits for controlling the block circuits over a predetermined floor, the following practice has been conventionally done: a net list of a logic circuit portion is generated and then control circuits are manually inserted; and after an arrangement and wiring process, a failure/no-failure test is conducted. Specifically, a device for verifying the correctness of layout after the generation of a net list is disclosed in Patent Document 1.
[Patent Document 1]
    Japanese Unexamined Patent Publication No. 2006-301786